Stream: Virtual Room 3
Time: 15:00 - 15:45
The speaker, an STSM in IBM Z Performance and Microprocessor Development, will discuss v5 (newly updated for z17) of The IBM Z Processor Optimization Primer document now available online. The platform's processor subsystems are described with focus on the core microarchitectures from z196 to z17. High level insights with information and potential methods to optimize for code performance will also be provided. Put on your propeller hat and come join us for a truly fascinating session!
David Hutton has been a part of IBM Z’s Microprocessor and Nest Performance teams, and Microprocessor Design and Verification teams with Poughkeepsie Engineering for 26 years. In his current role he is a client-facing lab representative for system performance inquiries and critical situations worldwide and develops the Large Systems Performance Reference (LSPR) and the MIPS and MSUs ratings. He has led and co-developed five generations of IBM Z core performance models that have helped to shape processor hardware designs and supply projection data to brand and marketing. He is an IBM STSM and Master Inventor and has co-authored roughly 30 patents.
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